![]() Uvm test will be a place where the uvm components such as uvm_env, uvm_agent, uvm_scoreboard will be constructed to create the testbench hierarchy. Then all the hdl path of your dut will start from this tb top and look like this: tb_module1.signal_a (where tb_top is the module name of the testbench top module) The testbench top will be passed to the EDA tool as top module in the compiling step. ![]()
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